Physical implementation: challenges and solutions

ing closure is very complex and can only be assured by accurately modeling and evaluating the propagation delays of the librar y cells, the physical placement of the cells and the electrical characteristics of the interconnect. Signal integrity has emerged as a determining factor to not only the timing, but to the functional integrity of the chip as well. As the ratio of cross-coupling capacitance to inter-layer capacitance increases, the rate of timing and functional violations due to signal integrity problems also rises. Other physical aspects such as antenna effects, electromigration, self-heating, and IR drop must also be analyzed and controlled throughout the chip construction process. While there are many design variable interdependencies to be dealt with, perhaps the most important is the trade-off between routability, timing, and power consumption. Optimizing for any one may cause problems with the others. An open objective function that can consider multiple objectives simultaneously is required to address these complex interdependencies. Clock and power networks consume massive amounts of routing resources. Their construction and analysis must be started early and they must be tailored for an individual chip’s requirements. Clock trees are frequently inserted after detailed placement is complete. Power networks are frequently pre-determined based on statistical or empirical estimates. However, these methods are showing increasing rates of non-convergence and are no longer adequate. Design sign-off lost its meaning in the mid-1990s. On a multi-million gate chip, it is not possible to sign-off on a netlist after completing logic design with a reasonable expectation that the physical implementation will meet all design requirements. Physical design is now as important as logic design in determining whether the requirements are achievable. Design size has exceeded the limitations of gate-level design tools. It is not possible to design and implement a multi-million gate chip as an indivisible whole. The chip must be planned at a high level, partiBy Olivier Coudert Senior Technologist Monterey Design Systems Inc. E-mail: [email protected]